PIC18F452-I/ML【PDF 47/134 页】IC MCU FLASH 16KX16 A/D 44QFN

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Sheet目录3813

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PIC16(L)F1508/9

DS41609A-page 234

Preliminary

2011 Microchip Technology Inc.

REGISTER 21-4:

SSPXCON3: SSP CONTROL REGISTER 3

R-0/0

R/W-0/0

ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

DHEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

ACKTIM:

Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock

0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock

bit 6

PCIE

: Stop Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled(2)

bit 5

SCIE

: Start Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Start or Restart conditions

0 = Start detection interrupts are disabled(2)

bit 4

BOEN:

Buffer Overwrite Enable bit

In SPI Slave mode:(1)

1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit

0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the

SSPxCON1 register is set, and the buffer is not updated

In I2C Master mode:

This bit is ignored.

In I2C Slave mode:

1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the

state of the SSPOV bit only if the BF bit = 0.

0 = SSPxBUF is only updated when SSPOV is clear

bit 3

SDAHT:

SDAx Hold Time Selection bit (I2C mode only)

1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

bit 2

SBCDE:

Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the

BCLxIF bit of the PIR2 register is set, and bus goes idle

1 = Enable slave bus collision interrupts

0 = Slave bus collision interrupts are disabled

bit 1

AHEN:

Address Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCLx for a matching received address byte, CKP bit of the

SSPxCON1 register will be cleared and the SCLx will be held low.

0 = Address holding is disabled

bit 0

DHEN:

Data Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCLx for a received data byte, slave hardware clears the CKP bit

of the SSPxCON1 register and SCLx is held low.

0 = Data holding is disabled

Note 1:

For daisy-chained SPI operation, allows the user to ignore all but the last received byte. SSPOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.

This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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